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Datasheet File OCR Text:

NAND04G-B2D, NAND08G-BxC
4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
Preliminary Data
Features
High density NAND Flash Memory - Up to 8 Gbit memory array - Cost-effective solution for mass storage applications NAND interface - x8 or 16x bus width - Multiplexed address/data Supply voltage: 1.8 V or 3.0 V device Page size - x8 device: (2048 + 64 spare) bytes - x16 device: (1024 + 32 spare) words Block size - x8 device: (128K + 4 K spare) bytes - x16 device: (64K + 2 K spare) words Multiplane architecture - Array split into two independent planes - Program/erase operations can be performed on both planes at the same time Page read/program - Random access: 25 s (max) - Sequential access: 25 ns (min) - Page program time: 200 s (typ) - Multiplane page program time (2 pages): 200 s (typ) Copy back program with automatic error detection code (EDC) Cache read mode Fast block erase - Block erase time: 1.5 ms (typ) - Multiblock erase time (2 blocks): 1.5 ms (typ) Status Register Electronic signature Chip Enable `don't care' Serial number option
NAND08G-BxC TSOP48 12 x 20 mm (N)
LGA

LGA52 12 x 17 mm (ZL)
r
Data protection: - Hardware program/erase disabled during power transitions - Non-volatile protection option ONFI 1.0 compliant command set Data integrity - 100 000 program/erase cycles (with ECC (error correction code)) - 10 years data retention ECOPACK(R) packages Device Summary
Part number NAND04GR3B2D

Table 1.
Reference

NAND04G-B2D
NAND04GW3B2D NAND04GR4B2D(1) NAND04GW4B2D(1) NAND08GR3B2C, NAND08GW3B2C NAND08GR4B2C(1) NAND08GW4B2C(1) NAND08GR3B4C NAND08GW3B4C

1. x16 organization only available for MCP products.
December 2007
Rev 3
1/69
www.numonyx.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
NAND04G-B2D, NAND08G-BxC
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 4.4 4.5 4.6 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 6.1.2 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2
Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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NAND04G-B2D, NAND08G-BxC
Contents
6.3
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1 6.3.2 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11
Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 P/E/R Controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 34 P/E/R Controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.12 6.13 6.14 6.15 6.16
Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read EDC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 8 9
Concurrent operations and extended read status . . . . . . . . . . . . . . . . 43 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 9.2 9.3 9.4 9.5 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48
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Contents
NAND04G-B2D, NAND08G-BxC
11 12
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.1 12.2 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 63 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13 14 15
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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NAND04G-B2D, NAND08G-BxC
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Address insertion (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Address insertion (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address definition (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address definition (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 EDC Status Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DC characteristics (1.8 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DC characteristics (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65 LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 66 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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List of figures
NAND04G-B2D, NAND08G-BxC
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 connections for NAND04G-B2D and NAND08G-BxC . . . . . . . . . . . . . . . . . . . . . 11 LGA52 connections for NAND04G-B2D and NAND08G-B2C devices. . . . . . . . . . . . . . . . 12 LGA52 connections for the NAND08G-B4C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cache read (random) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multiplane page program waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Copy back program (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Copy back program (with readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Equivalent testing circuit for AC characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 51 Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Sequential data output after read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Sequential data output after read AC waveforms (EDO mode) . . . . . . . . . . . . . . . . . . . . . 56 Read Status Register or read EDC Status Register AC waveform. . . . . . . . . . . . . . . . . . . 57 Read status enhanced waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Read Electronic Signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Read ONFI signature waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Page read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Read parameter page waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 64 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 65 LGA52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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NAND04G-B2D, NAND08G-BxC
Description
1
Description
The NAND04G-B2D and NAND08G-BxC are part of the NAND Flash 2112 byte/1056 word page family of non-volatile Flash memories. They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively. The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane), or to erase 2 blocks at a time (one in each plane). This feature reduces the average program and erase times by 50%. The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture. In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time. In the NAND08G-B4C devices, each NAND04G-B2D die can be accessed independently using two sets of signals. The devices operate from a 1.8 V or 3 V voltage supply. Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or or 1056 words (1024 + 32 spare), respectively. The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100 000 cycles with ECC (error correction code) on. To extend the lifetime of NAND Flash devices, the implementation of an ECC is strongly recommended. A Write Protect pin is available to provide hardware protection against program and erase operations. The devices feature an open-drain ready/busy output that identifies if the P/E/R (program/erase/read) Controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. An embedded error detection code is automatically executed after each copy back operation: 1 error bit can be detected for every 528 bits. With this feature it is no longer necessary, nor recommended, to use an external 2bit ECC to detect copy back operation errors. The devices have a cache read feature that improves the read throughput for large files. During cache reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O buffers to be read. The devices have the Chip Enable `don't care' feature, which allows code to be directly downloaded by a microcontroller. This is possible because Chip Enable transitions during the latency time do not stop the read operation. Both the NAND04G-B2D and NAND08G-BxC support the ONFI 1.0 specification.
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Description Two further features are available as options:

NAND04G-B2D, NAND08G-BxC
Extra non-volatile protection. An individual serial number that acts as an unique identifier.
More information is available, upon completion of an NDA (non-disclosure agreement), and therefore, the details are not described in this datasheet. For more information on these two options, contact your nearest Numonyx Sales office. The devices are available in the TSOP48 (12 x 20 mm) and LGA52 (12 x 17 mm) packages. To meet environmental requirements, Numonyx offers the NAND04G-B2D and NAND08GBxC in ECOPACK(R) packages. For information on how to order these options, refer to Table 34: Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to '1'. Table 2: Product description lists the part numbers and other information for all the devices able in the family. Table 2. Product description
Timings Part Number Density Bus width Page size Block size Memory array Operating voltage Sequential access time (min) 45 ns 25 ns 25 s 1.7 to 1.95 V 2.7 to 3.6 V 1.7 to 1.95 V 2.7 to 3.6 V 64 pages x 8192 blocks 1.7 to 1.95 V 2.7 to 3.6 V 1.7 to 1.95 V 2.7 to 3.6 V 45 ns
(1)
Random access time (max)
Page Program (typ)
Block Erase (typ)
Package
NAND04GR3B2D x8 NAND04GW3B2D 4 Gb NAND04GR4B2D x16 NAND04GW4B2D NAND08GR3B2C x8 NAND08GW3B2C NAND08GR4B2C 8 Gb NAND08GW4B2C NAND08GR3B4C NAND08GW3B4C x8 2048+64 bytes x8 128 K + 4 K bytes x16 1024+ 64 K + 32 words 2 K words 2048+64 bytes 128 K + 4 K bytes 1024+ 64 K + 32 words 2 K words 2048+64 bytes 128 K+ 4 K bytes 64 pages x 4096 blocks
1.7 to 1.95 V 2.7 to 3.6 V
LGA52 TSOP48 LGA52 200 s 1.5ms
25 ns 45 ns 25 ns 45 ns 25 s 25 ns 45 ns LGA52(2) 25 ns 200 s 1.5ms
(1)(2)
LGA52(2) TSOP48 LGA52(2)
1. x16 organization is only available for MCP products. 2. The NAND08G-BxC is composed of two 4-Gbit dice.
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NAND04G-B2D, NAND08G-BxC Figure 1. Logic block diagram
Description
Address Register/Counter AL CL W E WP R Command Register Page Buffer Cache Register Y Decoder Command Interface Logic P/E/R Controller, High Voltage Generator
X Decoder
NAND Flash Memory Array
I/O Buffers & Latches
RB I/O0-I/O7 (x8/x16) I/O8-I/O15 (x16)
AI13166b
1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die.
Figure 2.
Logic diagram
VDD
E R W AL CL WP NAND FLASH
I/O0-I/O7 (x8/x16) I/O8-I/O15 (x16)
RB
VSS
AI13167b
1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die.
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Description Table 3.
Signal I/O0-7 I/O8-15 AL CL E R RB W WP VDD VSS NC DU
NAND04G-B2D, NAND08G-BxC Signal names(1)
Function Data input/outputs, address inputs, or command inputs (x8/x16 devices) Data input/outputs (x16 devices) Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) Write Enable Write Protect Supply Voltage Ground Not connected internally Do not use Direction Input/output Input/output Input Input Input Input Output Input Input Power supply Ground N/A N/A
1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die.
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NAND04G-B2D, NAND08G-BxC Figure 3. TSOP48 connections for NAND04G-B2D and NAND08G-BxC
Description
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
12 37 NAND FLASH 13 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
24
25
AI13168b
11/69
Description Figure 4.
0
NAND04G-B2D, NAND08G-BxC LGA52 connections for NAND04G-B2D and NAND08G-B2C devices
1 2 3 4 5 6 7 8
OA
NC NC CL VSS AL NC NC NC WP NC I/O1 NC I/O2 I/O3 NC VSS NC NC NC VSS I/O4 VDD NC I/O6 I/O5 NC I/O0 NC I/O7 NC W RB VSS NC NC NC NC E VDD R NC
NC A NC B C NC D E F G H J NC K L M N
OB
NC
OC
NC
OD
NC
OE
NC
NC
OF
NC
NC
AI13634b
12/69
NAND04G-B2D, NAND08G-BxC Figure 5.
0
Description
LGA52 connections for the NAND08G-B4C devices
1 2 3 4 5 6 7 8
OA
NC NC CL1 VSS AL1 CL2 AL2 W2 WP1 I/O02 I/O11 I/O12 I/O21 I/O31 I/O22 VSS VSS NC I/O32 I/O42 I/O41 VDD NC I/O61 I/O51 I/O52 I/O01 WP2 I/O71 I/O62 W1 RB1 VSS I/O72 E2 R2 RB2 E1 VDD R1 NC
NC A NC B C NC D E F G H J NC K L M N
OB
NC
OC
NC
OD
NC
OE
NC
NC
OF
NC
NC
1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die.
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Memory array organization
NAND04G-B2D, NAND08G-BxC
2
Memory array organization
The memory array of the devices is made up of NAND structures where 32 cells are connected in series. It is organized into blocks where each block contains 64 pages. The array is split into two areas, the main area, and the spare area. The main area of the array is used to store data, and the spare area typically stores error correction codes, software flags, or bad block identification. In x8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes. In x16 devices, the pages are split into a 1024-word main area and a spare area of 32 words. Refer to Figure 6: Memory array organization.
Bad blocks
In the x8 devices, the NAND Flash 2112 byte/1056 word page devices may contain bad blocks, which are blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block information is written prior to shipping (refer to Section 9.1: Bad block management for more details). Table 4 shows the minimum number of valid blocks. The values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. Block 0 is guaranteed to be valid up to 1000 write/erase cycles with 1 bit ECC. These blocks need to be managed using bad blocks management, block replacement, or error correction codes (refer to Section 9: Software algorithms). Table 4. Valid Blocks
Density of Device 4 Gbits 8 Gbits(1) Min 4016 8032 Max 4096 8192
1. The NAND08G-BxC devices are composed of two 4-Gbit dice. The minimum number of valid blocks is 4016 for each die.
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NAND04G-B2D, NAND08G-BxC Figure 6. Memory array organization
Memory array organization
x8 bus width Plane = 2048 blocks, block = 64 pages, page = 2112 bytes (2048 + 64) First plane Second plane
a Sp
Main area Block Page
re
are
a a Sp
Main area
re
are
a
8 bits 2048 bytes 64 bytes 2048 bytes 64 bytes
Page buffer, 2112 bytes 2048 bytes
64 bytes
Page buffer, 2112 bytes 2,048 bytes
64 bytes
8 bits
2-page buffer, 2 x 2112 bytes
x16 bus width Plane = 2048 blocks, block = 64 pages, page = 1056 words (1024 + 32) First plane Second plane
S
Main area Block Page
re pa
are
a a Sp
Main area
re
are
a
16 bits 1024 words 32 words 1024 words 32 words
Page buffer, 1056 bytes 1024 words
32 words
Page buffer, 1056 bytes 1024 words
32 words
16 bits
AI13170b
2-page buffer, 2 x 1056 bytes
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Signal descriptions
NAND04G-B2D, NAND08G-BxC
3
Signal descriptions
See Figure 2: Logic diagram and Table 3: Signal names for a brief overview of the signals connected to this device. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or input a command or data during a write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled.
3.2
Inputs/Outputs (I/O8-I/O15)
Input/Outputs 8 to 15 are only available in x16 devices. They output the data during a read operation or input data during a write operation. Command and address inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled.
3.3
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
3.4
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.5
Chip Enable (E)
The Chip Enable input, E, activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, VIH, while the device is busy, the device remains selected and does not go into standby mode.
3.6
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one.
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NAND04G-B2D, NAND08G-BxC
Signal descriptions
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.
3.8
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.9
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that identifies if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes, Ready/Busy goes High, VOH. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Low then indicates that one or more of the memories is busy. During power-up and power-down a minimum recovery time of 10 s is required before the command interface is ready to accept a command. During this period the RB signal is Low, VOL. Refer to Section 12.1: Ready/Busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor.
3.10
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below VLKO (see Table 29) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1 F capacitor. The PCB track widths should be sufficient to carry the required program and erase currents.
3.11
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
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Bus operations
NAND04G-B2D, NAND08G-BxC
4
Bus operations
There are six standard bus operations that control the memory, as described in this section. See Table 5: Bus operations for a summary of these operations. Typically, glitches of less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 25 and Table 30 for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to input the addresses (refer to Table 6: Address insertion (x8 devices) and Table 7: Address insertion (x16 devices)). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low, and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 26 and Table 30 for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 27 and Table 30 and Table 31 for details of the timings requirements.
4.4
Data output
Data output bus operations read the data in the memory array, the Status Register, the electronic signature, and the unique identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal.
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NAND04G-B2D, NAND08G-BxC
Bus operations
If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the output data is latched on the rising edge of Read Enable signal (see Figure 28). For higher frequencies (tRLRL lower than 30 ns), the EDO (extended data out) mode must be used. In this mode, data output bus operations are valid on the input/output bus for a time of tRLQX after the falling edge of Read Enable signal (see Figure 29). See Table 31 for details on the timings requirements.
4.5
Write protect
Write protect bus operations protect the memory against program or erase operations. When the Write Protect signal is Low the device does not accept program or erase operations, and, therefore, the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled, and power consumption is reduced. Table 5. Bus operations
E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(2) X VIH X VIL VIL/VDD I/O0 - I/O7 Command Address Data input Data output X X I/O8 - I/O15(1) X X Data input Data output X X
Bus operation Command input Address input Data input Data output Write protect Standby
1. Only for x16 devices. 2. WP must be VIH when issuing a program or erase command.
Table 6.
Bus Cycle(1) 1st 2nd 3rd 4
th
Address insertion (x8 devices)
I/O7 A7 VIL A19 A27 VIL I/O6 A6 VIL A18 A26 VIL I/O5 A5 VIL A17 A25 VIL I/O4 A4 VIL A16 A24 VIL I/O3 A3 A11 A15 A23 VIL I/O2 A2 A10 A14 A22 A30(2) I/O1 A1 A9 A13 A21 A29 I/O0 A0 A8 A12 A20 A28
5th
1. Any additional address input cycles are ignored. 2. A30 is only valid for the NAND08G-BxC devices.
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Bus operations Table 7.
Bus Cycle(1) 1st 2
nd rd th
NAND04G-B2D, NAND08G-BxC Address insertion (x16 devices)
I/O7 A7 VIL A18 A26 VIL I/O6 A6 VIL A17 A25 VIL I/O5 A5 VIL A16 A24 VIL I/O4 A4 VIL A15 A23 VIL I/O3 A3 VIL A14 A22 VIL I/O2 A2 A10 A13 A21 A29(2) I/O1 A1 A9 A12 A20 A28 I/O0 A0 A8 A11 A19 A27
3
4
5th
1. Any additional address input cycles are ignored. 2. A29 is only valid for the NAND08G-BxC devices.
Table 8.
Address definition (x8 devices)
Address A0 - A11 A12 - A17 A18 - A29 A18 - A30 A18 = 0 A18 = 1 Definition Column address Page address Block address(NAND04G-B2D) Block address (NAND08G-BxC) First plane Second plane
Table 9.
Address definition (x16 devices)
Address A0 - A10 A11 - A16 A17 - A28 A17 - A29 A18 = 0 A18 = 1 Definition Column address Page address Block address (NAND04G-B2D) Block address (NAND08G-BxC) First plane Second plane
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NAND04G-B2D, NAND08G-BxC
Command set
5
Command set
All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security. Table 10 summarizes the commands. Table 10. Commands
Bus write operations Command(1) Read Random Data Output Cache Read (sequential) Enhanced Cache Read (random) Exit Cache Read Page Program (sequential input default) Random Data Input Multiplane Page Program(3) 1st cycle 00h 05h 31h 00h 3Fh 80h 85h 80h 80h 00h 85h Program(3) 85h 85h 60h Erase(3) 60h 60h FFh 90h 70h 78h ECh 7Bh 2nd cycle 30h E0h - 31h - 10h - 11h 11h 35h 10h 11h 11h D0h 60h D1h - - - - - - 3rd cycle - - - - - - - 81h 80h - - 81h 85h - D0h 60h - - - - - - 4th cycle - - - - - - - 10h 10h - - 10h 10h - - D0h - - - - - - Yes Yes Yes Yes(2) Commands accepted during busy
Multiplane Page Program Copy Back Read Copy Back Program Multiplane Copy Back
Multiplane Copy Back Program Block Erase Multiplane Block
Multiplane Block Erase Reset Read Electronic Signature Read Status Register Read Status Enhanced Read Parameter Page Read EDC Status Register
1. Commands in bold are referring to ONFI 1.0 specifications. 2. Only during cache read busy. 3. Command maintained for backward compatibility.
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Device operations
NAND04G-B2D, NAND08G-BxC
6
Device operations
This section provides details of the device operations.
6.1
Read memory array
At power-up the device defaults to read mode. To enter read mode from another mode, the Read command must be issued (see Table 10: Commands).
6.1.1
Random read
Each time the Read command is issued, the first read is random read.
6.1.2
Page read
After the first random read access, the page data (2112 bytes or 1056 words) are transferred to the page buffer in a time of tWHBH (see Table 31 ). Once the transfer is complete, the Ready/Busy signal goes High. The data can then be read sequentially (from selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during cache read operations.
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NAND04G-B2D, NAND08G-BxC Figure 7.
CL
Device operations
Read operations
E
W
AL
R tBLBH1 RB
I/O
00h
Command Code
Address Input
30h
Command Code
Data Output (sequentially)
Busy ai12469
23/69
Device operations Figure 8. Random data output during sequential data output
tBLBH1
(Read Busy time)
NAND04G-B2D, NAND08G-BxC
RB Busy W R tRHWL
I/O
00h Cmd Code
Address Inputs
30h Cmd Code
Data Output
05h Cmd Code
Address Inputs
E0h Cmd Code
Data Output
5 Add cycles Row Add 1,2,3 Col Add 1,2 Spare Area
2 Add cycles Col Add 1,2 Spare Area
Main Area
Main Area
ai08658b
6.2
Cache read
The cache read operation improves the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page into the Cache Register. A Read Page command, as defined in Section 6.1.1: Random read, is issued prior to the first Read Cache command in a read cache sequence. Once the data output of the Page Read command terminates, the Cache Read command can be issued as follows: 1. 2. Issue a Sequential Cache Read command to copy the next page in sequential order to the Cache Register. Issue a Random Cache Read command to copy the page addressed in this command to the Cache Register.
The two commands can be used interchangeably, in any order. When there are no more pages are to be read, the final page is copied into the Cache Register by issuing the Exit Cache Read command. A Read Cache Command must not be issued after the last page of the device is read. See Figure 9: Cache read (sequential) operation and Figure 10: Cache read (random) operation for examples of the two sequences.
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NAND04G-B2D, NAND08G-BxC
Device operations
After the Sequential Cache Read or Random Cache Read command has been issued, the Ready/Busy signal goes Low and the Status Register bits are set to SR5 =' 0' and SR6 ='0' for a period of Cache Read busy time, tRCBSY, while the device copies the next page into the Cache Register. After the cache read busy time has passed, the Ready/Busy signal goes High and the Status Register bits are set to SR5 = '0' and SR6 = '1', signifying that the Cache Register is ready to download new data. Data of the previously read page can be output from the page buffer by toggling the Read Enable signal. Data output always begins at column address 00h, but the Random Data Output command is also supported. Figure 9. Cache read (sequential) operation
RB
(Read Busy time)
tBLBH1
(Read Cache Busy time)
tRCBSY
(Read Cache Busy time)
tRCBSY
R
Busy I/O0-7
00h
Address Inputs
30h
31h
Data Outputs
3Fh
Data Outputs
Read Setup Code
Read Code
Cache Read Sequential Code Repeat as many times as ncessary.
Exit Cache Read Code
ai13176b
Figure 10. Cache read (random) operation
RB
(Read Busy time)
tBLBH1
(Read Cache Busy time)
tRCBSY
(Read Cache Busy time)
tRCBSY
R
Busy I/O0-7
00h
Address Inputs
30h
00h
Address Inputs
31h
Data Outputs
3Fh
Data Outputs
Read Setup Code
Read Code
Read Setup Code
Enhanced Cache Read (random) Code Repeat as many times as ncessary.
Exit Cache Read Code
ai13176c
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Device operations
NAND04G-B2D, NAND08G-BxC
6.3
Page program
The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however, the device does support random input within a page. It is recommended to address pages sequentially within a given block. The memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed. The maximum number of consecutive, partial-page program operations allowed in the same page is four. After exceeding four operations a Block Erase command must be issued before any further program operations can take place in that page.
6.3.1
Sequential input
To input data sequentially the addresses must be sequential and remain in one block. For sequential input each page program operation consists of the following five steps : 1. 2. 3. 4. 5. One bus cycle is required to set up the Page Program (sequential input) command (see Table 10: Commands). Five bus cycles are then required to input the program address (refer to Table 6: Address insertion (x8 devices) and Table 7: Address insertion (x16 devices)). The data is then loaded into the Data Registers. One bus cycle is required to issue the Page Program Confirm command to start the P/E/R Controller. The P/E/R only starts if the data has been loaded in step 3. the P/E/R Controller then programs the data into the array.
See Figure 11: Page program operation for more information.
6.3.2
Random data input in page
During a sequential input operation, the next sequential address to be programmed can be replaced by a random address by issuing a Random Data Input command. The following two steps are required to issue the command: 1. 2. One bus cycle is required to set up the Random Data Input command (see Table 10: Commands). Two bus cycles are then required to input the new column address (refer to Table 6: Address insertion (x8 devices)).
Random data input can be repeated as often as required in any given page. Once the program operation has started, the Status Register can be read using the Read Status Register command. During program operations the Status Register only flags errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands are accepted; all other commands are ignored. Once the program operation has completed, the P/E/R Controller bit SR6 is set to `1' and the Ready/Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the command interface.
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NAND04G-B2D, NAND08G-BxC Figure 11. Page program operation
(Program Busy time)
Device operations
tBLBH2
RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0
Read Status Register
ai08659
Figure 12. Random data input during sequential data input
(Program Busy time)
tBLBH2
RB Busy I/O 80h Cmd Code Address Inputs Data Intput 85h Cmd Code Address Inputs 2 Add cycles Col Add 1,2 Data Input 10h Confirm Code 70h SR0
Read Status Register
5 Add cycles Row Add 1,2,3 Col Add 1,2
Main Area
Spare Area
Main Area
Spare Area
ai08664
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Device operations
NAND04G-B2D, NAND08G-BxC
6.4
Multiplane page program
The devices support multiplane page program, which enables the programming of two pages in parallel, one in each plane. A multiplane page program operation requires the following two steps: 1. The first step serially loads up to two pages of data (4224 bytes) into the data buffer. It requires: - - - - One clock cycle to set up the Page Program command (see Section 6.3.1: Sequential input). 5 bus write cycles to input the first page address and data. The address of the first page must be within the first plane (A18 = 0). One bus write cycle to issue the Page Program Confirm code. After this, the device is busy for a time of tIPBSY. When the device returns to the ready state (Ready/Busy High), a multiplane page program setup code must be issued, followed by the 2nd page address (5 write cycles) and data. The address of the 2nd page must be within the second plane (A18 = 1).
2.
The 2nd step programs in parallel the two pages of data loaded into the data buffer into the appropriate memory pages. It is started by issuing a the Program Confirm command.
As for standard page program operation, the device supports random data input during both data loading phases. Once the multiplane page program operation has started, that is during a delay of tIPBSY, the Status Register can be read using the Read Status Register command. Once the multiplane page program operation has completed, the P/E/R Controller bit SR6 is set to `1' and the Ready/Busy signal goes High. If the multiplane page program fails, an error is signaled on bit SR0 of the Status Register. To know which page of the two planes failed, the Read Status Enhanced command must be issued twice, once for each plane (see Section 6.12). Figure 13 provides a description of multiplane page program waveforms. Figure 13. Multiplane page program waveform
tIPBSY RB Busy I/O 80h Address Inputs A18=0 Data Input 11h 80h(1) Address Inputs A18=1
(Program Busy time)
tBLBH2
Busy Data Input 10h Confirm Code 70h SR0
Page Program Setup Code
Confirm Multiplane Page Code Program Setup code
Read Status Register
ai13171b
1. The 81h setup code is also accepted for backward compatibility.
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NAND04G-B2D, NAND08G-BxC
Device operations
6.5
Copy back program
The copy back program operation copies the data stored in one page and reprograms it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC during a copy back operation. Consequently, external ECC is no longer required. The errors detected during copy back operations can be read by performing a read EDC Status Register operation (see Section 6.13: Read EDC Status Register). See also Section 6.9 for details of EDC operations. The copy back program operation requires the following four steps: 1. The first step reads the source page. The operation copies all 2112 bytes from the page into the data buffer. It requires: - - - 2. One bus write cycle to set up the command 5 bus write cycles to input the source page address One bus write cycle to issue the confirm command code
When the device returns to the ready state (Ready/Busy High), optional data readout is allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus cycles to input the target page address. See Table 11 for the addresses that must be the same for the source and target page. Issue the confirm command to start the P/E/R Controller.
3.
To see the data input cycle for modifying the source page and an example of the copy back program operation, refer to Figure 14: Copy back program (without readout of data). Figure 16: Page copy back program with random data input shows a data input cycle to modify a portion or a multiple distant portion of the source page. Table 11. Copy back program addresses
Density 4 Gbits 8 Gbits Source and target page addresses Same A18 Same A18 and A30
Figure 14. Copy back program (without readout of data)
I/O
00h Read Code
Source Add Inputs
35h
85h Copy Back Code
Target Add Inputs
10h
70h
SR0
Read Status Register tBLBH2
(Program Busy time)
tBLBH1
(Read Busy time)
RB Busy Busy
ai09858b
1. Copy back program is only permitted between odd address pages or even address pages.
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Device operations Figure 15. Copy back program (with readout of data)
I/O Source Add Inputs
NAND04G-B2D, NAND08G-BxC
00h Read Code
35h
Data Outputs
85h Copy Back Code
Target Add Inputs
10h
70h
SR0
Read Status Register tBLBH2
(Program Busy time)
tBLBH1
(Read Busy time)
RB Busy Busy
ai09858c
Figure 16. Page copy back program with random data input
I/O
00h Read Code
Source Add Inputs 35h
85h Copy Back Code
Target Add Inputs
Data
85h
2 Cycle Add Inputs
Data
10h
70h
SR0
Unlimited number of repetitions
tBLBH1
(Read Busy time)
tBLBH2
(Program Busy time)
RB Busy Busy
ai11001
6.6
Multiplane copy back program
In addition to multiplane page program, the NAND04G-B2D and NAND08G-BxC devices support multiplane copy back program. A Multiplane Copy Back Program command requires exactly the same steps as a Multiplane Page Program command, and must satisfy the same time constraints (see Section 6.4: Multiplane page program). Prior to executing the multiplane copy back program operation, two single-page read operations must be executed to copy back the first page from the first plane and the second page from the second plane. The EDC check is also performed during the multiplane copy back program. Errors during multiplane copy back operations can be detected by performing a Read EDC Status Register operation (see Section 6.13: Read EDC Status Register). If the multiplane copy back program fails, an error is signaled on bit SR0 of the Status Register. To know which page of the two planes failed, the Read Status Enhanced command must be executed twice, once for each plane (see Section 6.12).
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NAND04G-B2D, NAND08G-BxC
Device operations
Figure 17 provides a description of multiplane copy back program waveform. Figure 17. Multiplane copy back program
I/O
00h Read Code
Source Add Inputs 35h A18=0 tBLBH1
(Read Busy time)
00h Read Code
Source 35h Add Inputs A18 = 1 tBLBH1
(Read Busy time)
85h
Target Add Inputs
11h
85h(1)
Target Add Inputs
10h
70h
SR0
Copy Back A18 = 0 Code tIPBSY
Copy Back A18 = 1 Code
Read Status Register tBLBH2
(Program Busy time)
RB Busy Busy Busy Busy
ai13172b
1. The 81h setup code is also accepted for backward compatibility.
6.7
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to `1'. All previous data in the block is lost. An erase operation consists of the following three steps (refer to Figure 18: Block erase): 1. 2. 3. One bus cycle is required to set up the Block Erase command. Only addresses A18A29 are used; all other address inputs are ignored. Three bus cycles are then required to load the address of the block to be erased. Refer to Table 8: Address definition (x8 devices) for the block addresses of each device. One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R Controller.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command is issued. The P/E/R Controller handles block erase and implements the verify process. During the block erase operation, only the Read Status Register and Reset commands are accepted; all other commands are ignored. Once the program operation has completed, the P/E/R Controller bit SR6 is set to `1' and the Ready/Busy signal goes High. If the operation completed successfully, the Write Status bit SR0 is `0', otherwise it is set to `1'. Figure 18. Block erase
tBLBH3
(Erase Busy time)
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0
Read Status Register
ai07593
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Device operations
NAND04G-B2D, NAND08G-BxC
6.8
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. This operation consists of the following three steps (refer to Figure 19: Multiplane block erase): 1. 8 bus cycles are required to set up the Block Erase command and load the addresses of the blocks to be erased. The setup command followed by the address of the block to be erased must be issued for each block. tIEBSY busy time is required between the insertion of first and the second block addresses. As for multiplane page program operations, the address of the first and second page must be within the first plane (A18 = 0) and second plane (A8 = 1), respectively. One bus cycle is then required to issue the Multiplane Block Erase Confirm command and start the P/E/R Controller.
2.
If the multiplane block erase fails, an error is signaled on bit SR0 of the Status Register. To know which page of the two planes failed, the Read Status Enhanced command must be issued twice, once for each plane (see Section 6.12). Figure 19. Multiplane block erase
tIEBSY RB Busy I/O 60h Block Erase Setup Code Block Address Inputs A18 = 0 D1h(1) 60h Block Address Inputs A18 = 1 D0h Confirm Code 70h SR0 tBLBH3
(Erase Busy time)
Multiplane Block Block Erase Setup Code Erase Code
Read Status Register
ai13173b
1. The D1h Confirm code is required by the ONFI 1.0 command set. To maintain backward compatibility, the D1h Confirm code can optionally be ignored, and then the tIEBSY Busy Time does not occur.
6.9
Error detection code (EDC)
The EDC (error detection code) is performed automatically during all program operations. It starts immediately after the device becomes busy. The EDC detects 1 single bit error per EDC unit. Each EDC unit has a density of 528 bytes (or 264 words), split into 512 bytes of main area and 16 bytes of spare area (or 256 + 8 words). Refer to Table 12 and Figure 20 for EDC unit addresses definition. To properly use the EDC, the following conditions apply:

Page program operations must be performed on a whole page, or on whole EDC unit(s). The modification of the content of an EDC unit using a random data input before the copy back program, must be performed on the whole EDC unit. It can only be done once per EDC unit. Any partial modification of the EDC unit results in the corruption of the on-chip EDCs.
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NAND04G-B2D, NAND08G-BxC
Device operations
EDC results can be retrieved only during copy back program and multiplane copy back using the Read EDC Status Register command (see Section 6.13). Figure 20. Page organization
Page = 4 EDC units Main area (2048 bytes/1024 words) Spare area (64 bytes/32 words)
A area B area C area D area (512 bytes/ (512 bytes/ (512 bytes/ (512 bytes/ 256 words) 256 words) 256 words) 256 words)
E area (16 bytes/ 8 words)
F area G area (16 bytes/ (16 bytes/ 8 words) 8 words)
H area (16 bytes/ 8 words)
AI13179b
Table 12.
Address definition for EDC units (x8 devices)
Main area Spare area Area name E F G H Column address 2048 to 2063 2064 to 2079 2080 to 2095 2096 to 2111
EDC unit Area name 1st 528-byte EDC unit 2nd 528-byte EDC unit 3rd 528-byte EDC unit 4th 528-byte EDC unit A B C D Column address 0 to 511 512 to 1023 1024 to1535 1536 to 2047
Table 13.
Address definition for EDC units (x16 devices)
Main area Spare area Area name E F G H Column address 1024 to 1031 1032 to 1039 1040 to 1047 1048 to 1055
EDC unit Area name 1st 264-word EDC unit 2nd 264-word EDC unit 3rd 264-word EDC unit 4th 264-word EDC unit A B C D Column address 0 to 255 256 to 511 512 to 767 768 to 1023
6.10
Reset
The Reset command is used to reset the command interface and Status Register. If the Reset command is issued during any operation, the operation is aborted. If the aborted operation is a program or erase, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. If the device has already been reset, then the new Reset command is not accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued. Refer to Table 31 for the values.
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Device operations
NAND04G-B2D, NAND08G-BxC
6.11
Read Status Register
The devices contain a Status Register that provides information on the current or previous program or erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore, if a Read Status Register command is issued during a Random Read cycle, a new Read command must be issued to continue with a page read operation. The Status Register bits are summarized in Table 14: Status Register bits. Refer to Table 14 in conjunction with the following sections.
6.11.1
Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is set to `1', the device is not protected and program or erase operations are allowed. If the write protection bit is set to `0' the device is protected and program or erase operations are not allowed.
6.11.2
P/E/R Controller and cache ready/busy bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation. During cache operations, SR6 acts as a cache ready/busy bit, which indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy, and when SR6 is set to '1', the Cache Register is ready to accept new data. During all other operations, SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready).
6.11.3
P/E/R Controller bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive during cache operations. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready).
Note:
This bit is only valid for cache operations.
6.11.4
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R Controller. The error bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to `0' the operation has completed successfully.
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NAND04G-B2D, NAND08G-BxC
Device operations
6.11.5
Table 14.
Bit SR7
SR4, SR3, SR2 and SR1 are reserved
Status Register bits
Name Write protection '0' Protected P/E/R Controller inactive, device ready P/E/R Controller active, device busy P/E/R Controller inactive, device ready P/E/R Controller active, device busy Program/Erase/Read Controller Program/Erase/Read Controller(1) Reserved '1' '0' '1' '0' `don't care' `1' Error - operation failed No error - operation successful Logic level '1' Not protected Definition
SR6
SR5 SR4, SR3, SR2, SR1 SR0
Generic error `0'
1. Only valid for cache operations.
6.12
Read status enhanced
In NAND Flash devices with multiplane architecture, it is possible to independently read the Status Register of a single plane using the Read Status Enhanced command. If the Error bit of the Status Register, SR0, reports an error during or after a multiplane operation, the Read Status Enhanced command is used to know which of the two planes contains the page that failed the operation. Three address cycles are required to address the selected block and page (A18-0). The output of the Read Status Enhanced command has the same coding as the Read Status command. See Table 14 for a full description and Figure 31 for the read status enhanced waveform.
6.13
Read EDC Status Register
The devices contain an EDC Status Register, which provides information on the errors that occurred during the read cycles of the copy back and multiplane copy back operations. In the case of multiplane copy back program, it is not possible to distinguish which of the two read operations caused the error. The EDCS Status Register is read by issuing the Read EDC Status Register command. After issuing the Read EDC Status Register command, a read cycle outputs the content of the EDC Status Register to the I/O pins on the falling edge of Chip Enable or Read Enable signals, whichever occurs last. The operation is similar to Read Status Register command. Table 15: EDC Status Register bits summarizes the EDC Status Register bits. See Figure 30 for a description of Read EDC Status Register waveforms.
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Device operations Table 15.
Bit
NAND04G-B2D, NAND08G-BxC EDC Status Register bits
Name Logic level `1' 0 Pass/fail `0' `1' 1 EDC status `0' `1' 2 3 4 5 EDC validity `0' Reserved Reserved Ready/busy(1) `don't care' `don't care' `1' `0' 6 Ready/busy(1) `1' `0' `1' 7 Write protect `0' Protected Invalid Ready Busy Ready Busy Not protected No error Valid Copy back or multiplane copy back operation succeeded Error Definition Copy back or multiplane copy back operation failed
1. See Table 14: Status Register bits for a description of SR5 and SR6 bits.
6.14
Read electronic signature
The devices contain a manufacturer code and device code. The following three steps are required to read these codes: 1. 2. 3. One bus write cycle to issue the Read Electronic Signature command (90h) One bus write cycle to input the address (00h) Five bus read cycles to sequentially output the data (as shown in Table 16: Electronic signature).
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NAND04G-B2D, NAND08G-BxC Table 16. Electronic signature
Byte 1 Byte 2 Byte 3 (see Table 17) 10h 10h 10h 10h 51h 51h 51h 51h Byte 4
Device operations
Root part number NAND04GR3B2D NAND08GR3B4C(1) NAND04GW3B2D NAND08GW3B4C(1) NAND04GR4B2D NAND04GW4B2D NAND08GR3B2C NAND08GW3B2C NAND08GR4B2C NAND08GW4B2C
Byte 5 (see Table 19) 54h 54h 54h 54h 58h 58h 58h 58h
(see Table 18) 15h 95h 55h D5h 15h 95h 55h D5h
20h 20h 0020h 0020h 20h 20h 0020h 0020h
ACh DCh BCh CCh A3h D3h B3h C3h
1. For NAND08G-B4C devices, each 4 Gb die returns its own electronic signature.
Table 17.
I/O
Electronic signature byte 3
Definition Value 00 01 10 11 00 01 10 11 00 01 10 11 0 1 0 1 Description 1 2 4 8 2-level cell 4-level cell 8-level cell 16-level cell 1 2 4 8 Not supported Supported Not supported Supported
I/O1-I/O0
Internal chip number
I/O3-I/O2
Cell type
I/O5-I/O4
Number of simultaneously programmed pages
I/O6 I/O7
Interleaved programming between multiple devices Cache program
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Device operations Table 18.
I/O
NAND04G-B2D, NAND08G-BxC
Electronic signature byte 4
Definition Value 00 01 10 11 0 1 00 10 01 11 00 01 10 11 0 1 Description 1 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes 8 16 30/50 ns 25 ns Reserved Reserved 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes x8 x16
I/O1-I/O0
Page size (without spare area) Spare area size (byte/512 byte)
I/O2
I/O7, I/O3
Minimum sequential access time
I/O5-I/O4
Block size (without spare area)
I/O6
Organization
Table 19.
Electronic signature byte 5
I/O I/O1 - I/O0 Definition Reserved Value 00 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 plane 2 planes 4 planes 8 planes 64 Mbits 128 Mbits 256 Mbits 512 Mbits 1 Gb 2 Gb 4 Gb 8 Gb Description
I/O3 - I/O2
Plane number
I/O6 - I/O4
Plane size (without spare area)
I/O7
Reserved
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NAND04G-B2D, NAND08G-BxC
Device operations
6.15
Read ONFI signature
To recognize NAND Flash devices that are compatible with the ONFI 1.0 command set, the Read Electronic Signature can be issued, followed by an address of 20h. The next four bytes output is the ONFI signature, which is the ASCII encoding of the "ONFI" word. Reading beyond four bytes produces indeterminate values. Figure 33 provides a description of the read ONFI signature waveform and Table 20 provides the definition of the output bytes. Table 20. Read ONFI signature
Byte 1st byte 2nd byte 3rd byte 4th byte 5th byte Value 4Fh 4Eh 46h 49h Undefined ASCII character O N F I Undefined
6.16
Read parameter page
The Read Parameter Page command retrieves the data structure that describes the NAND Flash organization, features, timings and other behavioral parameters. This data structure enables the host processor to automatically recognize the NAND Flash configuration of a device. The whole data structure is repeated at least five times. See Figure 40 for a description of the read parameter page waveform. The Random Data Read command can be issued during execution of the read parameter page to read specific portions of the parameter page. The Read Status command may be used to check the status of read parameter page during execution. After completion of the Read Status command, 00h is issued by the host on the command line to continue with the data output flow for the Read Parameter Page command. Read status enhanced is not be used during execution of the Read Parameter Page command. Table 21 defines the parameter page data structure; for parameters that span multiple bytes, the least significant byte of the parameter corresponds to the first byte. Values are reported in the parameter page in bytes when referring to items related to the size of data access (as in an x8 data access device). For example, the chip returns how many data bytes are in a page. For a device that supports x16 data access, the host is required to convert byte values to word values for its use. Unused fields are set to 0h. For more detailed information about parameter page data bits, refer to ONFI Specification 1.0, section 5.4.1.
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Device operations Table 21.
Byte
NAND04G-B2D, NAND08G-BxC Parameter page data structure
O/M(1) Parameter page signature - Byte 0: 4Fh, "O" - Byte 1: 4Eh, "N" - Byte 2: 46h, "F" - Byte 3: 49h, "I" Revision number 4-5 M Bit 2 to bit 15 Reserved (0) Bit 1 1 = supports ONFI version 1.0 Reserved (0) Features supported Bit 5 to bit 15 Reserved (0) Bit 4 6-7 M Bit 3 Bit 2 Bit 1 Bit 0 1 = supports odd to even page copyback 1 = supports interleaved operations 1 = supports non-sequential page programming 1 = supports multiple LUN operations 1 = supports 16-bit data bus width Optional commands supported Bit 6 to bit 15 Reserved (0) Bit 5 8-9 M Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10-31 1 = supports Read Unique ID 1 = supports Copyback 1 = supports Read Status Enhanced 1 = supports Get Features and Set Features 1 = supports Read Cache commands 1 = supports Page Cache Program command Reserved (0) M M M O Device manufacturer (12 ASCII characters) Device model (20 ASCII characters) JEDEC manufacturer ID Date code Reserved (0) M M M M M Number of data bytes per page Number of spare bytes per page Number of data bytes per partial page Number of spare bytes per partial page Number of pages per block Description
0-3
M
Revision information and features block
Bit 0
Manufacturer information block 40/69
32-43 44-63 64 65-66 67-79 80-83 84-85 86-89 90-91 92-95
NAND04G-B2D, NAND08G-BxC Table 21.
Byte 96-99 100
Device operations
Parameter page data structure (continued)
O/M(1) M M Description Number of blocks per logical unit (LUN) Number of logical units (LUNs) Number of address cycles
101
M
Bit 4 to bit 7 Bit 0 to bit 3
Column address cycles Row address cycles Number of bits per cell Bad blocks maximum per LUN Block endurance Guaranteed valid blocks at beginning of target Block endurance for guaranteed valid blocks Number of programs per page Partial programming attributes
102 103-104 105-106 107 108-109 Memory organization block 110
M M M M M M
Bit 5 to bit 7 111 M 4 Bit 1 to bit 3 0 112 M
Reserved 1 = partial page layout is partial page data followed by partial page spare Reserved 1 = partial page programming has constraints Number of bits ECC correctability Number of interleaved address bits
113
M
Bit 4 to bit 7 Bit 0 to bit 3
Reserved (0) Number of interleaved address bits Interleaved operation attributes
Bit 4 to bit 7 114 O Bit 3 Bit 2 Bit 1 Bit 0 115-127 128 M
Reserved (0) Address restrictions for program cache 1 = program cache supported 1 = no block address restrictions Overlapped/concurrent interleaving support Reserved (0) I/O pin capacitance
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Device operations Table 21.
Byte
NAND04G-B2D, NAND08G-BxC Parameter page data structure (continued)
O/M(1) Description Timing mode support Bit 6 to bit 15 Reserved (0) Bit 5 129-130 M Bit 4 Bit 3 Bit 2 1 = supports timing mode 5 1 = supports timing mode 4 1 = supports timing mode 3 1 = supports timing mode 2 1 = supports timing mode 1 1 = supports timing mode 0, shall be 1 Program cache timing mode support Bit 6 to bit 15 Reserved (0) Bit 5 131-132 O Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 133-134 135-136 137-138 139-163 M M M M M M M M M O 1 = supports timing mode 5 1 = supports timing mode 4 1 = supports timing mode 3 1 = supports timing mode 2 1 = supports timing mode 1 1 = supports timing mode 0 tPROG maximum page program time (s) tBERS maximum block erase time (s) tR maximum page read time (s) Reserved (0) Vendor specific revision number Vendor specific Integrity CRC Value of bytes 0-255 Value of bytes 0-255 Additional redundant parameter pages
Electrical parameters block
Bit 1 Bit 0
Vendor block Red. param. pages 42/69
164-165 166-253 254-255 256-511 512-767 768+
1. O = optional, M = mandatory
NAND04G-B2D, NAND08G-BxC
Concurrent operations and extended read status
7
Concurrent operations and extended read status
The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This configuration allows the devices to support concurrent operations, which means that while performing an operation in one die (erase, read, program, etc.), another operation is possible in the other die. The standard Read Status Register operation returns the status of the NAND08G-BxC device. To provide information on each 4-Gbit die, the NAND08G-BxC devices feature an Extended Read Status Register command that independently checks the status of each NAND04G-B2D. The following steps are required to perform concurrent operations: 1. 2. 3. 4. Select one of the two dice by setting the most significant address bit A30 to `0' or `1'. Execute one operation on this die. Launch a concurrent operation on the other die. Check the status of these operations by performing an Extended Read Status Register operation.
All combinations of operations are possible except read while read. This is due to the fact that the input/output bus is common to both dice. Refer to Table 22 for the description of the Extended Read Status Register command sequence, and to Table 14. for the definition of the Status Register bits. Table 22. Extended Read Status Register commands
Address range Address 0x3FFFFFFF 0x3FFFFFFF < Address 0x7FFFFFF 1 bus write cycle F2h F3h
Command Read 1st die status Read 2nd die status
8
Data protection
The devices feature a Write Protect, WP, pin, which can be used to protect the device against program and erase operations. It is recommended to keep WP at VIL during powerup and power-down.
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Software algorithms
NAND04G-B2D, NAND08G-BxC
9
Software algorithms
This section provides information on the software algorithms that Numonyx recommends implementing to manage the bad blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunnelling using high voltage. Exposing the device to high voltage for extended periods damages the oxide layer. To extend the number of program and erase cycles and increase the data retention, the:

Number of program and erase cycles is limited (see Table 24: Program erase times and program erase endurance cycles for the values) Implementation of a garbage collection, a wear-leveling algorithm and an error correction code is recommended.
To help integrate a NAND memory into an application, Numonyx provides a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details.
9.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices that have all valid blocks. A bad block does not affect the performance of valid blocks because it is isolated from the bit and common source lines by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The bad block information is written prior to shipping. Any block, where the 1st and 6th bytes or the 1st word in the spare area of the 1st page, does not contain FFh, is a bad block. The bad block information must be read before any erase is attempted as the bad block Information may be erased. For the system to be able to recognize the bad blocks based on the original information, the creation of a bad block table following the flowchart shown in Figure 21: Bad block management flowchart is recommended.
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NAND04G-B2D, NAND08G-BxC
Software algorithms
9.2
NAND Flash memory failure modes
Over the lifetime of the device bad blocks may develop. To implement a highly reliable system, the possible failure modes must be considered.
Program/erase failure In this case, the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified because attempts to program or erase them gives errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by reprogramming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See Section 6.5: Copy back program for more details.
Read failure In this case, ECC correction must be implemented. To efficiently use the memory space, the recovery of a single-bit error in read by ECC, without replacing the whole block, is recommended.
Refer to Table 23: Block failure for the recommended procedure to follow if an error occurs during an operation. Table 23. Block failure
Operation Erase Program Read Procedure Block replacement Block replacement or ECC ECC
Figure 21. Bad block management flowchart
START
Block Address = Block 0
Increment Block Address Update Bad Block table
Data = FFh? YES
NO
Last block? YES
NO
END
AI07588C
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Software algorithms
NAND04G-B2D, NAND08G-BxC
9.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, resulting in the previous page being marked as invalid. After several updates it is necessary to remove invalid pages to free memory space. To free this memory space and allow further program operations, the implementation of a garbage collection algorithm is recommended. In garbage collection software, the valid pages are copied into a free area and the block containing the invalid pages is erased as show in Figure 22. Figure 22. Garbage collection
Old Area New Area (After GC)
Valid Page Invalid Page Free Page (Erased)
AI07599B
9.4
Wear-leveling algorithm
For write-intensive applications, the implementation of a wear-leveling algorithm is recommended to monitor and spread the number of write cycles per block. In memories that do not use a wear-leveling algorithm, not all blocks get used at the same rate. The wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels:

First level wear-leveling, where new data is programmed to the free blocks that have had the fewest write cycles. Second level wear-leveling, where long-lived data is copied to another block so that the original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
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NAND04G-B2D, NAND08G-BxC
Software algorithms
9.5
Error correction code
An ECC can be implemented in the NAND Flash memories to identify and correct errors in the data. For every 2048 bits in the device, the implementation of 22 bits of ECC (16 bits for line parity plus 6 bits for column parity) is recommended. Figure 23. Error detection
New ECC generated during read
XOR previous ECC with new ECC
All results = zero? YES 22 bit data = 0
NO
>1 bit = zero? YES 11 bit data = 1
NO
1 bit data = 1
No Error
Correctable Error
ECC Error
ai08332
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Program and erase times and endurance cycles
NAND04G-B2D, NAND08G-BxC
10
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown in Table 24. Table 24. Program erase times and program erase endurance cycles
NAND Flash Parameters Min Page Program/Multiplane Program time Block Erase/Multiplane Erase time Multiplane Program time (1.8 V) Multiplane Erase (1.8 V) Multiplane Program Busy time (tIPBSY) Multiplane Erase Busy time (tIEBSY) Cache Read Busy time (tRCBSY) Program/erase cycles per block (with ECC) Data retention 100 000 10 Typ 200 1.5 250 2 0.5 0.5 3 Max 700 2 800 2.5 1 1 tR s ms s ms s s s Cycles Years Unit
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NAND04G-B2D, NAND08G-BxC
Maximum ratings
11
Maximum ratings
Stressing the device above the ratings listed in Table 25: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer to the Numonyx SURE Program and other relevant quality documents for more information. Table 25.
Symbol TBIAS TSTG VIO(1) VDD
Absolute maximum ratings
Value Parameter Min Temperature under bias Storage temperature Input or output voltage Supply voltage - 50 - 65 - 0.6 - 0.6 Max 125 150 4.6 4.6 C C V V Unit
1. Minimum voltage may undershoot to -2 V for less than 20 ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
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DC and AC parameters
NAND04G-B2D, NAND08G-BxC
12
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the devices. The parameters in the following DC and AC characteristics tables are derived from tests performed under the measurement conditions summarized in Table 26. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 26. Operating and AC measurement conditions
NAND Flash Parameter Min Supply voltage (VDD) Grade 1 Ambient temperature (TA) Load capacitance (CL) (1 TTL GATE and CL) Input pulses voltages Input and output timing ref. voltages Output circuit resistor Rref Input rise and fall times Grade 6 1.8 V device 3.0 V device 2.7 0 -40 30 50 0 VDD/2 8.35 5 VDD Max 3.6 70 85 V C C pF pF V V k ns Units
Table 27.
Symbol CIN CI/O
Capacitance(1)
Parameter Input capacitance Input/output capacitance(2) Test condition VIN = 0V VIL = 0V Typ Max 10 10 Unit pF pF
1. TA = 25C, f = 1MHz. CIN and CI/O are not 100% tested. 2. Input/output capacitances double in stacked devices.
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NAND04G-B2D, NAND08G-BxC Figure 24. Equivalent testing circuit for AC characteristics measurement
VDD
DC and AC parameters
2Rref
NAND Flash
CL
2Rref
GND
GND
Ai11085
Table 28.
Symbol IDD1 IDD2 IDD3 IDD5 ILI ILO VIH VIL VOH VOL IOL (RB) VLKO
DC characteristics (1.8 V devices)
Parameter Sequential read Program Erase Standby current (CMOS(1)) Input leakage current(1) Output leakage current(1) Test conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT= 0 to VDDmax IOH = -100 A IOL = 100 A VOL = 0.1 V Min 0.8 * VDD -0.3 VDD - 0.1 3 Typ 10 10 10 10 Max 20 20 20 50 10 10 VDD + 0.3 0.2 * VDD 0.1 4 1.2 Unit mA mA mA A A A V V V V mA V
Operating current
Input high voltage Input low voltage Output high voltage level Output low voltage level Output low current (RB) VDD supply voltage (erase and program lockout)
1. Leakage current and standby current double in stacked devices.
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DC and AC parameters Table 29.
Symbol IDD1 IDD2 IDD3
IDD4
NAND04G-B2D, NAND08G-BxC
DC characteristics (3 V devices)
Parameter Sequential read Program Erase Standby current (TTL)
(1)
Test conditions tRLRL minimum E = VIL, IOUT = 0 mA E = VIH, WP = 0/VDD E = VDD-0.2, WP = 0/VDD VIN= 0 to VDDmax VOUT= 0 to VDDmax IOH = -400 A IOL = 2.1 mA VOL = 0.4 V -
Min -
Typ 15 15 15
Max 30 30 30 1
Unit mA mA mA mA A A A V V V V mA V
Operating current
IDD5 ILI ILO VIH VIL VOH VOL IOL (RB) VLKO
Standby current (CMOS)(1) Input leakage current(1) Output leakage current(1)
0.8 VDD -0.3 2.4 8 -
10 -
50 10 10 VDD+0.3 0.2 VDD 0.4 10 1.8
Input High voltage Input Low voltage Output High voltage Level Output Low voltage Level Output Low current (RB) VDD supply voltage (erase and program lockout)
1. leakage current and standby current double in stacked devices.
Table 30.
Symbol tALLWH tALHWH tCLHWH tCLLWH tDVWH tELWH tWHALH tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL
AC characteristics for command, address, data input
Alt. Symbol tALS Parameter Address Latch Low to Write Enable high AL setup time Address Latch High to Write Enable high Command Latch High to Write Enable high tCLS tDS tCS tALH tCLH tDH tCH tWH tWP tWC CL setup time Command Latch Low to Write Enable high Data Valid to Write Enable High Chip Enable Low to Write Enable high Write Enable High to Address Latch High Write Enable High to Command Latch High CL hold time Write Enable High to Command Latch Low Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data hold time E hold time W high hold time W pulse width Write cycle time Min Min Min Min Min 10 10 15 25 45 5 5 10 12 25 ns ns ns ns ns Min 10 5 ns Data setup time E setup time AL hold time Min Min Min 20 35 10 12 20 5 ns ns ns Min 25 12 ns Min 25 12 ns 1.8 V 3V Unit
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NAND04G-B2D, NAND08G-BxC Table 31.
Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 tPROG tBERS Ready/Busy Low to Ready/Busy High tBLBH4 tRST
DC and AC parameters
AC characteristics for operations(1)
Alt. symbol tAR tRR Address Latch Low to Read Enable Low Parameter Read electronic signature Read cycle Min Min Min Max Max Max Max Max Max Max Min Min Max Min Chip Enable High to Command Latch `don't care' Read Enable High to Output Hi-z Chip Enable Low to Output Valid Read Enable High to Read Enable Low Read Enable High Hold time Max Max Min Min Min Min Min Min 100 45 15 15 15 5 25 45 100 25 10 15 15 5 12 25 ns ns ns ns ns ns ns ns 1.8 V 10 10 20 25 700 2 5 5 10 500 10 0 30 10 3V 10 10 20 25 700 2 5 5 10 500 10 0 30 10 Unit ns ns ns s s ms s s s s ns ns ns ns
Ready/Busy High to Read Enable Low Read Busy time Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read Reset Busy time, during program Reset Busy time, during erase
tCLLRL tDZRL tEHQZ tEHALX tEHCLX tRHQZ tELQV tRHRL tEHQX tRHQX tRLQX tRLRH tRLRL tRLQV tWHBH tWHBL tWHRL tRHWL
tCLR tIR tCHZ tCSD tRHZ tCEA tREH tCOH tRHOH tRLOH tRP tRC tREA tR tWB tWHR tRHW
Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Output Hi-Z Chip Enable High to Address Latch `don't care'
Chip Enable high to Output Hold Read Enable High to Output Hold Read Enable Low to Output Hold (EDO mode) Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable pulse width Read cycle time Read Enable access time Read ES access time(2) Read Busy time
Max
30
20
ns
Max Max Min Min
25 100 60 100
25 100 60 100
s ns ns ns
Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Read Enable High to Write Enable Low
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DC and AC parameters Table 31.
tWHWH tVHWH tVLWH
NAND04G-B2D, NAND08G-BxC
AC characteristics for operations(1) (continued)
tADL(3) tWW(4) Last address latched to data loading time during program operations Write protection time Min Min 100 100 70 100 ns ns
1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figure 41, Figure 42 and Figure 43. 2. ES = Electronic Signature. 3. tADL is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
4. During a Program/Erase Enable Operation, tWW is the delay from WP high to W High. During a Program/Erase Disable Operation, tWW is the delay from WP Low to W High.
Figure 25. Command latch AC waveforms
CL tCLHWH
(CL Setup time)
tWHCLL
(CL Hold time)
tELWH
H(E Setup time)
tWHEH
(E Hold time)
E tWLWH W tALLWH
(ALSetup time)
tWHALH
(AL Hold time)
AL tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai12470b
54/69
NAND04G-B2D, NAND08G-BxC Figure 26. Address latch AC waveforms
DC and AC parameters
(CL Setup time)
tCLLWH
CL tELWH
(E Setup time)
tWLWL
tWLWL
tWLWL
tWLWL
E tWLWH W tWHWL tALHWH
(AL Setup time)
tWLWH
tWLWH
tWLWH
tWLWH
tWHWL
tWHWL
tWHWL
tWHALL
(AL Hold time)
tWHALL
tWHALL
tWHALL
AL tDVWH tDVWH tWHDX
(Data Hold time)
(Data Setup time)
tDVWH tWHDX Adrress cycle 2 Adrress cycle 3
tDVWH tWHDX Adrress cycle 4
tDVWH tWHDX Adrress cycle 5
ai12471
tWHDX
I/O
Adrress cycle 1
Figure 27. Data input latch AC waveforms
tWHCLH
(CL Hold time)
CL tWHEH
(E Hold time)
E
(ALSetup time)
tALLWH
tWLWL AL tWLWH W tDVWH
(Data Setup time)
tWLWH
tWLWH
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX tWHDX
I/O
Data In 0
Data In 1
Data In Last
ai12472
1. The last data input is the 2112th.
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DC and AC parameters Figure 28. Sequential data output after read AC waveforms
NAND04G-B2D, NAND08G-BxC
tRLRL
(Read Cycle time)
E tEHQX tRHRL R
(R High Holdtime)
tEHQZ
tRHQZ tRLQV
(R Accesstime)
tRHQZ tRLQV tRHQX(2)
tRLQV
I/O tBHRL RB
Data Out
Data Out
Data Out
ai13174
1. CL = Low, AL = Low, W = High. 2. tRHQX is applicable for frequencies lower than 33MHz (i.e. tRLRL higher than 30ns).
Figure 29. Sequential data output after read AC waveforms (EDO mode)
tRLRL E tEHQX tRLRH R tELQV tRLQV
(R Accesstime)
tRHRL
tEHQZ
tRLQX tRLQV
tRHQZ tRHQX(2)
I/O tBHRL RB
Data Out
Data Out
Data Out
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH. 2. tRLQX is applicable for frequencies high than 33 MHz (i.e. tRLRL lower than 30 ns).
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NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 30. Read Status Register or read EDC Status Register AC waveform
tCLLRL CL tWHCLL tCLHWH E tELWH tWLWH W tWHRL R tDZRL tDVWH
(Data Setup time)
tWHEH
tELQV
tEHQZ tEHQX
tRHQZ tRLQV tRHQX
tWHDX
(Data Hold time)
I/O
70h or 7Bh
Status Register Output
ai13177
Figure 31. Read status enhanced waveform
CL
W
AL R
I/O0-7
78h
Address 1
Address 2
Address 3
Status Register Output
ai14408
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DC and AC parameters Figure 32. Read Electronic Signature AC waveform
CL
NAND04G-B2D, NAND08G-BxC
E
W
AL tALLRL1
R
(Read ES Access time)
tRLQV
I/O
90h Read Electronic Signature Command
00h 1st Cycle Address
Byte1 Man. code
Byte2 Device code
Byte3
Byte4
Byte5
see Note.1
ai13178
1. Refer to Table 16 for the values of the manufacturer and device codes, and to Table 17, Table 18, and Table 19 for the information contained in byte 3, byte 4, and byte 5.
Figure 33. Read ONFI signature waveform
CL
E
W
AL tALLRL1
R
(Read ES access time)
tRLQV
I/O
90h Read Electronic Signature command
20h 1st cycle address
4Fh
4Eh
46h
49h
XXh
ai13178b
58/69
NAND04G-B2D, NAND08G-BxC Figure 34. Page read operation AC waveform
DC and AC parameters
CL
tEHALX tEHCLX
E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL
(Read Cycle time)
tEHQZ
tRHQZ
R tRLRH tBLBH1 RB
I/O
00h
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N cycle 4
Add.N cycle 5
30h
Data N
Data N+1
Data N+2
Data Last
Command Code
Address N Input
Busy
Data Output from Address N to Last Byte or Word in Page
ai12474b
59/69
DC and AC parameters Figure 35. Page program AC waveform
CL
NAND04G-B2D, NAND08G-BxC
E
tWLWL
(Write Cycle time)
tWLWL
tWLWL
W tWHWH tWHBL tBLBH2
(Program Busy time)
tWHRL
AL
R
I/O
80h
Add.N cycle 1
Add.N Add.N Add.N Add.N cycle 2 cycle 3 cycle 4 cycle 5
N
Last
10h
70h
SR0
RB Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program Read Status Register
ai12475b
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NAND04G-B2D, NAND08G-BxC Figure 36. Block erase AC waveform
DC and AC parameters
CL
E tWLWL
(Write Cycle time)
W tWHBL AL
(Erase Busy time)
tBLBH3
tWHRL
R
I/O
60h
Add. Add. Add. cycle 1 cycle 2 cycle 3
D0h
70h
SR0
RB Block Erase Setup Command Confirm Code Block Erase Read Status Register
ai08038c
Block Address Input
Figure 37. Reset AC waveform
W
AL CL
R I/O FFh tBLBH4
(Reset Busy time)
RB
ai08043
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DC and AC parameters Figure 38. Program/erase enable waveform
NAND04G-B2D, NAND08G-BxC
W tVHWH WP
RB
I/O
80h
10h
ai12477
Figure 39. Program/erase disable waveform
W tVLWH WP High RB
I/O
80h
10h
ai12478
Figure 40. Read parameter page waveform
CL
W
AL
R
I/O0-7
ECh
00h tBLBH1
P00
P10
...
P01
P11
...
R/B
ai14409
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NAND04G-B2D, NAND08G-BxC
DC and AC parameters
12.1
Ready/Busy signal electrical characteristics
Figure 42, Figure 41 and Figure 43 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation:
(V - ) DDmax V OLmax R P min = ------------------------------------------------------------+ IL I OL
This is an example for 3 V devices:
3,2V R P min = -------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 41. Ready/Busy AC waveform
ready VDD VOH VOL busy tf tr
AI07564B
Figure 42. Ready/Busy load circuit
VDD
RP
ibusy
DEVICE RB Open Drain Output
VSS
AI07563B
63/69
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 43. Resistor value versus waveform timings for Ready/Busy signal
VDD = 3.3 V, CL = 50 pF 200
200 2.4
4
150
tr, tf (ns)
1.2
150
3
ibusy (mA)
100
100 0.8
2
50
50 1.8 1.8
1
0.6 1.8
0
1.8
1
2 RP (K) tf tr
3
4
ibusy
ai12476
1. T = 25C.
12.2
Data protection
The Numonyx NAND devices aredesigned to guarantee data protection during power transitions. A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold. In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept low (VIL) to guarantee hardware protection during power transitions as shown in the below figure. Figure 44. Data protection
VDD
Nominal Range
VLKO
Locked
Locked
W
Ai11086
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NAND04G-B2D, NAND08G-BxC
Package mechanical
13
Package mechanical
Figure 45. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1 48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
1. Drawing is not to scale.
Table 32.
Symbol
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
Millimeters Typ Min Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.080 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0276 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283
A A1 A2 B C CP D1 E E1 e L L1 a
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Package mechanical
NAND04G-B2D, NAND08G-BxC
Figure 46. LGA52 12 x 17 mm, 1 mm pitch, package outline
D D2 D1 FE1 FE FD FD1
BALL "A1"
eE1
E E2
E1 e ddd
e A
b1 b2 A2
LGA-9G
Table 33.
LGA52 12 x 17 mm, 1 mm pitch, package mechanical data
Millimeters Inches Max 0.650 0.650 0.700 1.000 12.000 6.000 10.000 0.100 17.000 12.000 13.000 1.000 2.000 3.000 1.000 2.500 2.000 - - - - 16.900 17.100 0.6693 0.4724 0.5118 0.0394 0.0787 0.1181 0.0394 0.0984 0.0787 - - - - 0.6654 0.650 0.950 11.900 0.750 1.050 12.100 0.0276 0.0394 0.4724 0.2362 0.3937 0.0039 0.6732 0.0256 0.0374 0.4685 Typ Min Max 0.0256 0.0256 0.0295 0.0413 0.4764
Symbol Typ A A2 b1 b2 D D1 D2 ddd E E1 E2 e eE1 FD FD1 FE FE1 Min
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NAND04G-B2D, NAND08G-BxC
Part numbering
14
Part numbering
Table 34.
Example: Device type NAND Flash memory Density 04 G = 4 Gb 08 G = 8 Gb Operating voltage W = VDD = 2.7 to 3.6 V R = VDD = 1.7 to 1.95 V Bus width 3 = x8 4 = x16(1) Family identifier B = 2112 byte page Device options 2 = Chip Enable `don't care' enabled 4 = Chip Enable `don't care' enabled with dual interface Product version C= Third version (NAND08G-BxC) D = Fourth version (NAND04G-B2D) Package N = TSOP48 12 x 20 mm ZL = LGA52 12 x 17 mm Temperature range 1 = 0 to 70 C 6 = -40 to 85 C Option E = ECOPACK package, standard packing F = ECOPACK package, tape and reel packing
1. x16 organization only available for MCP products
Ordering information scheme
NAND04GW3B2D N 6 E
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest Numonyx Sales Office.
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Revision history
NAND04G-B2D, NAND08G-BxC
15
Revision history
Table 35.
Date 22-June-2007
Document revision history
Revision 1 Initial release. Added the part numbers NAND08GR3B4C, NAND08GW3B4C, therefore referring to the 8 Gbit devices as the NAND08G-BxC. Modified all data throughout this document to reflect the addition of these part numbers, namely: - Table 1, Table 2, Table 6, and Table 34. - Added Figure 5: LGA52 connections for the NAND08G-B4C devices. Changed VLKO value in Table 28 from 1.1 to 1.2. Applied Numonyx branding. Changes
17-Sep-2007
2
10-Dec-2007
3
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NAND04G-B2D, NAND08G-BxC
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